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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 lm73605-q1/lm73606-q1 3.5-v to 36-v, 5-a or 6-a synchronous step-down voltage converter 1 1 features 1 ? aec-q100 qualified for automotive applications ? device temperature grade 1: ? 40 c to +125 c junction operating temperature ? device hbm esd classification level 2 kv ? device cdm esd classification level c5 ? wettable flanks qfn package (wqfn) ? low emi and low switching noise ? low quiescent current ? 0.8 a in shutdown (typical) ? 15 a in active mode with no load (typical) ? wide voltage conversion range: ? t on-min = 60 ns (typical) ? t off-min = 70 ns (typical) ? low mosfet on-resistance: ? r ds_on_hs = 53 m ? (typical) ? r ds_on_ls = 31 m ? (typical) ? adjustable frequency range: 350 khz to 2.2 mhz ? pin-selectable auto mode or forced pwm mode ? start-up into pre-biased load, fixed or adjustable soft-start time, and tracking ? synchronizable to external clock, internal compensation, power-good flag, and precision enable ? cycle-by-cycle current limiting, hiccup, uvlo, and thermal shutdown protections ? create a custom design with the webench ? power designer using lm73605-q1 or lm73606- q1 simplified schematic 2 applications ? automotive distributed power applications ? battery-powered applications ? general-purpose wide v in applications 3 description the lm73605-q1/lm73606-q1 family of devices are easy-to-use synchronous step-down dc-dc converters capable of driving up to 5 a (lm73605- q1) or 6 a (lm73606-q1) of load current from a supply voltage ranging from 3.5 v to 36 v. the lm73605-q1/lm73606-q1 provide exceptional efficiency and output accuracy in a very small solution size. peak current-mode control is employed. additional features such as adjustable switching frequency, synchronization to an external clock, fpwm option, power-good flag, precision enable, adjustable soft start, and tracking provide both flexible and easy-to-use solutions for a wide range of applications. automatic frequency foldback at light load and optional external bias improve efficiency over the entire load range. the family requires few external components and has a pinout designed for simple pcb layout with optimal emi and thermal performance. protection features include thermal shutdown, input undervoltage lockout, cycle-by-cycle current limiting, and hiccup short-circuit protection. the lm73605-q1 and lm73606-q1 devices are pin- to-pin compatible for easy current scaling. device information (1) part number package body size (nom) lm73605-q1 wqfn (30) wettable flanks 6.00 mm 4.00 mm lm73606-q1 (1) for all available packages, see the orderable addendum at the end of the data sheet. efficiency vs load current v out = 5 v, v in = 12 v, auto mode sw pvin pgnd cboot vcc bias en agnd fb v in c out c boot c in c vcc v out r fbt r fbb l sync/ mode rt ss/trk pgood copyright ? 2017, texas instruments incorporated load current (a) efficiency (%) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 50 55 60 65 70 75 80 85 90 95 100 eff_ freq = 400 khz freq = 2.2 mhz tools & software technical documents ordernow productfolder support &community
2 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 6 6.5 electrical characteristics ........................................... 6 6.6 timing characteristics ............................................... 7 6.7 switching characteristics .......................................... 8 6.8 system characteristics ............................................. 8 6.9 typical characteristics .............................................. 9 7 detailed description ............................................ 11 7.1 overview ................................................................. 11 7.2 functional block diagram ....................................... 11 7.3 feature description ................................................. 12 7.4 device functional modes ........................................ 24 8 application and implementation ........................ 26 8.1 application information ............................................ 26 8.2 typical application ................................................. 26 9 power supply recommendations ...................... 44 10 layout ................................................................... 44 10.1 layout guidelines ................................................. 44 10.2 layout example .................................................... 47 11 device and documentation support ................. 48 11.1 device support ...................................................... 48 11.2 related documentation ....................................... 48 11.3 related links ........................................................ 48 11.4 receiving notification of documentation updates 48 11.5 community resources .......................................... 49 11.6 trademarks ........................................................... 49 11.7 electrostatic discharge caution ............................ 49 11.8 glossary ................................................................ 49 12 mechanical, packaging, and orderable information ........................................................... 49 4 revision history date revision notes november 2017 * initial release
3 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) a = analog, o = output, i = input, g = ground, p = power 5 pin configuration and functions rnp package 30-pin wettable flanks qfn (wqfn) 6 mm 4 mm 0.8 mm top view pin functions pin i/o (1) description no. name 1, 2, 3, 4, 5 sw p switching output of the regulator. internally connected to source of the hs fet and drain of the ls fet. connect to power inductor and bootstrap capacitor. 6 cboot p bootstrap capacitor connection for hs fet driver. connect a high-quality 470-nf capacitor from this pin to the sw pin. 7 vcc p output of internal bias supply. used as supply to internal control circuits and drivers. connect a high-quality 2.2- f capacitor from this pin to gnd. ti does not recommend loading this pin by external circuitry. 8 bias p optional bias ldo supply input. ti recommends tying to v out when 3.3 v v out 18 v, or tie to an external 3.3-v or 5-v rail if available, to improve efficiency. bias pin voltage must not be greater than v in . tie to ground when not in use. 9 rt a switching frequency setting pin. place a resistor from this pin to ground to set the switching frequency. if floating, the default switching frequency is 500 khz. do not short to ground. 10 ss/trk a soft-start control pin. leave this pin floating for a 5-ms internal soft-start ramp. an external capacitor can be connected from this pin to ground to extend the soft start time. a 2- a current sourced from this pin charges the capacitor to provide the ramp. connect to external ramp for tracking. do not short to ground. 11 fb i feedback input for output voltage regulation. connect a resistor divider to set the output voltage. never short this pin to ground during operation. 12 ? 15, 27 ? 30 nc ? no internal connection. connect to ground net and copper to improve heat sinking and board-level reliability. 16 pgood o open drain power-good flag output. connect to suitable voltage supply through a current limiting resistor. high = v out regulation ok, low = v out regulation fault. pgood = low when en = low and v in > 2 v. vcc rt bias ss/trk 2 3 4 23 25 24 pvin swsw dap pvin pgnd sw 22 26 1 5 cboot sw pgnd 21 6 pgnd pgnd 20 7 pgood 19 8 agnd 9 10 18 17 en fb sync/ mode 16 11 29 28 27 30 13 14 15 12 sw pvin nc nc nc nc nc nc nc nc
4 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin i/o (1) description no. name 17 sync/mode i synchronization input and mode setting pin. do not float. tie to ground if not used. tie to ground: auto mode, higher efficiency at light loads; tie to logic high: forced pwm, constant switching frequency over load; tie to external clock source: forced pwm, synchronize to the rising edge of the external clock. 18 en i enable input to regulator. do not float. high = on, low = off. can be tied to pvin. precision enable input allows adjustable input voltage uvlo using external resistor divider. 19 agnd g analog ground. ground reference for internal circuitry. all electrical parameters are measured with respect to this pin. connect to system ground on pcb. 20 ? 22 pvin p supply input to internal bias ldo and hs fet. connect to input supply and input bypass capacitors c in . c in must be placed right next to this pin and pgnd pins on pcb, and connected with short and wide traces. 23 ? 26 pgnd g power ground, connected to the source of ls fet internally. connect to system ground, dap/ep, agnd, ground side of c in and c out on pcb. path to c in must be as short as possible ep dap g low impedance connection to agnd. connect to system ground on pcb. major heat dissipation path for the device. must be used for heat sinking by soldering to ground copper on pcb. thermal vias are preferred to improve heat dissipation to other layers.
5 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range of ? 40 c to +125 c (unless otherwise noted) (1) parameter min max unit input voltages pvin to pgnd ? 0.3 42 v en to agnd ? 0.3 v in + 0.3 fb, rt, ss/trk to agnd ? 0.3 5 pgood to agnd ? 0.1 20 sync to agnd ? 0.3 5.5 bias to agnd ? 0.3 lower of (v in + 0.3) or 20 agnd to pgnd ? 0.3 0.3 output voltages sw to pgnd ? 0.3 v in + 0.3 v sw to pgnd less than 10-ns transients ? 3.5 42 cboot to sw ? 0.3 5 vcc to agnd ? 0.3 5 operating junction temperature, t j ? 40 150 c storage temperature, t stg ? 65 150 c (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per aec q100-011 750 v (1) recommended operating rating indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. for ensured specifications, see electrical characteristics 6.3 recommended operating conditions over operating free-air temperature range of ? 40 c to +125 c (unless otherwise noted) (1) min max unit input voltages pvin to pgnd 3.5 36 v en 0 v in fb 0 4.5 pgood 0 18 bias input not used 0 0.3 bias input used 0 lower of (v in + 0.3) or 18 agnd to pgnd ? 0.1 0.1 output voltage v out 1 95% of v in v output current i out , lm73605-q1 0 5 a i out , lm73606-q1 0 6 a temperature operating junction temperature, t j ? 40 125 c
6 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) lm73605/lm73606 unit rnp (wqfn) 30 pins r ja junction-to-ambient thermal resistance 34.3 c/w r jc(top) junction-to-case (top) thermal resistance 14.6 c/w r jb junction-to-board thermal resistance 7.3 c/w jt junction-to-top characterization parameter 0.1 c/w jb junction-to-board characterization parameter 7.1 c/w r jc(bot) junction-to-case (bottom) thermal resistance 1 c/w (1) shutdown current includes leakage current of the switching transistors. 6.5 electrical characteristics limits apply over the recommended operating junction temperature (t j ) range of ? 40 c to +125 c, unless otherwise stated. minimum and maximum limits are specified through test, design or statistical correlation. typical values represent the most likely parametric norm at t j = 25 c, and are provided for reference purposes only. unless otherwise stated, v in = 12 v. parameter test conditions min typ max unit supply voltage (pvin pins) v in operating input voltage range 3.5 36 v i sd shutdown quiescent current; measured at vin pin (1) v en = 0 v t j = 25 0.8 10 a i q_nonsw operating quiescent current from v in (non-switching) v en = 2 v, v fb = 1.5 v, v bias = 3.3 v external 0.6 12 a enable (en pin) v en_vcc_h enable input high level for v cc output v en rising 1.15 v v en_vcc_l enable input low level for v cc output v en falling 0.3 v v en_vout_h enable input high level for v out v en rising 1.14 1.196 1.25 v v en_vout_hys enable input hysteresis for v out v en falling hysteresis ? 100 mv i lkg_en enable input leakage current v en = 2 v 1.4 200 na internal ldo (vcc pin, bias pin) v cc internal v cc voltage pwm operation 3.27 v pfm operation 3.1 v v cc_uvlo internal v cc undervoltage lockout v cc rising 2.96 3.14 3.27 v v cc falling hysteresis ? 605 mv v bias_on input changeover v bias rising 3.09 3.25 v v bias falling hysteresis ? 63 mv i bias_nonsw operating quiescent current from external v bias (non- switching) v en = 2 v, v fb = 1.5 v, v bias = 3.3 v external 21 50 a voltage reference (fb pin) v fb feedback voltage pwm mode 0.987 1.006 1.017 v i lkg_fb input leakage current at fb pin v fb = 1 v 0.2 60 na
7 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) limits apply over the recommended operating junction temperature (t j ) range of ? 40 c to +125 c, unless otherwise stated. minimum and maximum limits are specified through test, design or statistical correlation. typical values represent the most likely parametric norm at t j = 25 c, and are provided for reference purposes only. unless otherwise stated, v in = 12 v. parameter test conditions min typ max unit (2) this current limit was measured as the internal comparator trip point. due to inherent delays in the current limit comparator and drivers, the peak current limit measured in closed loop with faster slew rate will be larger, and valley current limit will be lower. (3) measured at pins (4) ensured by design high side driver (cboot pin) v cboot_uvlo cboot - sw undervoltage lockout 1.6 2.2 2.7 v current limits and hiccup i hs_limit short-circuit, high-side current limit (2) lm73605-q1 6 7.3 8.35 a lm73606-q1 7.4 8.7 9.85 i ls_limit low-side current limit (2) lm73605-q1 4.79 5.5 6.1 a lm73606-q1 5.8 6.6 7.25 i neg_limit negative current limit lm73605-q1 ? 5 a lm73606-q1 ? 6 v hiccup hiccup threshold on fb pin 0.36 0.4 0.44 v i l_zc zero cross-current limit 0.06 a soft start (ss/trk pin) i ssc soft-start charge current 1.8 2 2.2 a r ssd soft-start discharge resistance uvlo, tsd, ocp, or en = 0 1 k power good (pgood pin) and overvoltage protection v pgood_ov power-good overvoltage threshold % of fb voltage 106% 110% 113% v pgood_uv power-good undervoltage threshold % of fb voltage 86% 90% 93% v pgood_hys power-good hysteresis % of fb voltage 1.2% v pgood_valid minimum input voltage for proper pgood function 50- a pullup to pgood pin, v en = 0 v, t j = 25 c 1.3 2 v r pgood power-good on-resistance v en = 2.5v 40 100 v en = 0 v 30 90 mosfets r ds_on_hs (3) high-side mosfet on- resistance i out = 1 a, v bias = v out = 3.3 v 53 90 m ? r ds_on_ls (3) low-side mosfet on- resistance i out = 1 a, v bias = v out = 3.3 v 31 55 m ? thermal shutdown t sd (4) thermal shutdown threshold shutdown threshold 160 c recovery threshold 135 c (1) ensured by design 6.6 timing characteristics min nom max unit current limits and hiccup n oc (1) number of switching cycles before hiccup is tripped 128 cycles t oc overcurrent hiccup retry delay time 46 ms
8 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated timing characteristics (continued) min nom max unit soft start (ss/trk pin) t ss internal soft-start time c ss = open, from en rising edge to pgood rising edge 3.5 6.3 ms power good (pgood pin) and overvoltage protection t pgood_rise pgood rising edge deglitch delay 80 140 200 s t pgood_fall pgood falling edge deglitch delay 80 140 200 s 6.7 switching characteristics parameter test conditions min typ max unit pwm limits (sw pins) t on-min minimum switch on-time 60 82 ns t off-min minimum switch off-time 70 120 ns t on-max maximum switch on-time hs timeout in dropout 3 6 9 s oscillator (rt and sync pins) f osc internal oscillator frequency r t = open 440 500 560 khz f adj minimum adjustable frequency by r t or sync r t =115 k , 0.1% 315 350 385 khz maximum adjustable frequency by r t or sync r t = 17.4 k , 0.1% 1980 2200 2420 khz v sync_high sync input high level threshold 2 v v sync_low sync input low level threshold 0.4 v v mode_high mode input high level threshold for fpwm 0.42 v v mode_low mode input low level threshold for auto mode 0.4 v t sync_min sync input minimum on and off- time 80 ns 6.8 system characteristics the following specifications apply to the circuit found in typical schematic with appropriate modifications from typical bill of materials . these parameters are not tested in production and represent typical performance only. unless otherwise stated the following conditions apply: t a = 25 c, v in = 12 v, v out = 3.3 v, f sw = 500 khz. parameter test conditions min typ max unit v fb_pfm output voltage offset at no load in auto mode v in = 3.8 v to 36 v, v sync = 0 v, auto mode i out = 0 a 2% v drop minimum input to output voltage differential to maintain specified accuracy v out = 5 v, i out = 3 a, f sw = 2.2 mhz 0.4 v i q_sw operating quiescent current (switching) v en = 3.3 v, i out = 0 a, r t = open, v bias = v out = 3.3 v , r fbt = 1 meg 15 a i peak_min minimum inductor peak current lm73605-q1: v sync = 0, i out = 10 ma 1 a lm73606-q1: v sync = 0 v, i out = 10 ma 1.3 i bias_sw operating quiescent current from external v bias (switching) f sw = 500 khz, i out = 1 a 7 ma f sw = 2.2 mhz, i out = 1 a 25 d max maximum switch duty cycle while in frequency foldback 97.5% t dead dead time between high-side and low-side mosfets 4 ns
9 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.9 typical characteristics unless otherwise specified, v in = 12 v. curves represent most likely parametric norm at specified condition. figure 1. high-side and low-side switches r ds-on figure 2. shutdown quiescent current figure 3. feedback voltage figure 4. lm73605 -q1 high-side and low-side current limits figure 5. lm73606 -q1 high-side and low-side current limit figure 6. switching frequency set by r t resistor temperature (c) rds-on (m : ) -40 -20 0 20 40 60 80 100 120 140 20 25 30 35 40 45 50 55 60 65 70 75 char hs switch ls switch temperature (c) shutdown current (na) -40 -20 0 20 40 60 80 100 120 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 plotplotchar vin = 3.5 v vin = 12 v vin = 36 v vin (v) feedback voltage (v) 3 6 9 12 15 18 21 24 27 30 33 36 1 1.001 1.002 1.003 1.004 1.005 1.006 1.007 1.008 1.009 1.01 char temp = -40c temp = 25c temp = 125c temperature (c) current limits (a) -40 -20 0 20 40 60 80 100 120 5 5.5 6 6.5 7 7.5 char hs ls temperature (c) frequency (khz) -40 -20 0 20 40 60 80 100 120 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 char freq = 350 khz freq = 1 mhz freq = 2.2 mhz temperature (c) current limits (a) -40 -20 0 20 40 60 80 100 120 6 6.6 7.2 7.8 8.4 9 char hs ls
10 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) unless otherwise specified, v in = 12 v. curves represent most likely parametric norm at specified condition. figure 7. switching frequency with rt pin open circuit figure 8. enable thresholds figure 9. pgood thresholds temperature (c) pgood thresholds (%) -40 -20 0 20 40 60 80 100 120 85 90 95 100 105 110 115 char ov tripping ov recovery uv recovery uv tripping temperature (c) frequency with rt pin floating (khz) -40 -20 0 20 40 60 80 100 120 450 460 470 480 490 500 510 520 530 540 550 char vin = 3.5 v vin = 12 v vin = 36 v temperature (c) enable thresholds (v) -40 -20 0 20 40 60 80 100 120 140 0.56 0.64 0.72 0.8 0.88 0.96 1.04 1.12 1.2 1.28 char ven_vout rising ven_vout falling ven_vcc rising ven_vcc falling
11 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7 detailed description 7.1 overview the lm73605-q1/6-q1 is an easy-to-use synchronous step-down dc-dc converter that operates from a 3.5-v to 36-v supply voltage. it is capable of delivering up to 5-a (lm73605-q1) or 6-a (lm73606-q1) dc load current with exceptional efficiency and thermal performance in a very small solution size. the lm73605-q1/6-q1 employs fixed-frequency peak current-mode control with configurable auto or fpwm operation mode. auto mode provides very high efficiency at light loads, and fpwm mode maintains constant switching frequency over entire load range. the device is internally compensated, which reduces design time and the number of external components. the switching frequency is programmable from 350 khz to 2.2 mhz by an external resistor. the lm73605-q1/6-q1 can also synchronize to an external clock within the same frequency range. the wide switching frequency range allows the device to be optimized for a wide range of system requirements. it can be optimized for small solution size with higher frequency; or for high efficiency with lower switching frequency. the lm73605-q1/6-q1 has very low quiescent current, which is critical for battery operated systems. it allows for a wide range of voltage conversion ratios due to very small minimum on-time (t on-min ) and minimum off-time (t off-min ). automated frequency foldback is employed at very high or low duty cycles to further extend the operating range. the lm73605-q1/6-q1 also features a power-good (pgood) flag, precision enable, internal or adjustable soft start, pre-biased start-up, and output voltage tracking. protection features include thermal shutdown, undervoltage lockout (uvlo), cycle-by-cycle current limiting, and short-circuit hiccup protection. it provides flexible and easy-to-use solutions for a wide range of applications. the family requires very few external components and has a pin out designed for simple, optimum pcb layout for enhanced emi and thermal performance. the lm73605-q1/6-q1 device is available in a 30-pin wqfn leadless package. 7.2 functional block diagram ref pvin bias pgood enable control logic agnd pgnd oscillator ldo sync/ mode vcc sw fb hs i sense ea rt uvlo hiccup detector internal ss ov/uv detector + pfm detector slope comp + precision enable ls i sense pgood fb r c c c i ssc + i cmd i limit + v cc clk fpwm tsd v boot v boot uvlo ss/trk copyright ? 2017, texas instruments incorporated cboot v sw v sw
12 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3 feature description 7.3.1 synchronous step-down regulator the lm73605-q1/6-q1 is a synchronous buck converter with both power mosfets integrated in the device. figure 10 shows a simplified schematic for synchronous and non-synchronous buck converters. the synchronous buck integrates both high-side (hs) and low-side (ls) power mosfets. the non-synchronous buck integrates hs mosfet and works with a discrete power diode as ls rectifier. figure 10. simplified synchronous vs non-synchronous buck converters a synchronous converter with integrated hs and ls mosfets offers benefits such as less design effort, lower external components count, reduced total solution size, higher efficiency at heavier load, easier pcb design, and more control flexibility. the main advantage of a synchronous converter is that the voltage drop across the ls mosfet is lower than the voltage drop across the power diode of a non-synchronous converter. lower voltage drop translates into less power dissipation and higher efficiency. the lm73605-q1/6-q1 integrates hs and ls mosfets with very low on-time resistance to improve efficiency. it is especially beneficial when the output voltage is low. because the ls mosfet is integrated into the device, at light loads a synchronous converter has the flexibility to operate in either discontinuous or continuous conduction mode. an integrated ls mosfet also allows the controller to obtain inductor current information when the ls switch is on. it allows the control loop to make more complex decisions based on hs and ls currents. it allows the lm73605-q1/6-q1 to have peak and valley cycle-by-cycle current limiting for more robust protection. 7.3.2 auto mode and fpwm mode the lm73605-q1/6-q1 has configurable auto mode or fpwm options. in auto mode, the device operates in diode emulation mode (dem) at light loads. in dem, inductor current stops flowing when it reaches 0 a. this is also referred to as discontinuous conduction mode (dcm). this is the same behavior as the non-synchronous regulator, with higher efficiency. at heavier load, when the inductor current valley is above 0 a, the device operates in continuous conduction mode (ccm), where the switching frequency is fixed and set by rt pin. in auto mode, the peak inductor current has a minimum limit, i peak_min , in the lm73605-q1/6-q1. when peak current reaches i peak_min , the switching frequency reduces to regulate the required load current. switching frequency lowers when load reduces. this is when the device operates in pulse frequency modulation (pfm). pfm further improves efficiency by reducing switching losses. light load efficiency is especially important for battery operated systems. in forced pwm (fpwm) mode, the device operates in ccm regardless of load with the frequency set by rt pin or synchronization input. inductor current can go negative at light loads. at light loads, the efficiency is lower than auto mode, due to higher conduction losses and switching losses. in fpwm, the device has fixed switching frequency over the entire load range, which is beneficial to noise sensitive applications. figure 11 shows the inductor current waveforms in each mode with heavy load, light load, and very light load. the difference between the two modes is at lighter loads where inductor current valley reaches zero. sw vin pgnd pgnd c in v in c out v out l synchronous buck sw vin c in v in c out v out l non synchronous buck copyright ? 2017, texas instruments incorporated
13 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) figure 11. inductor current waveforms at auto mode and fpwm mode with different loads in ccm, the inductor current peak-to-peak ripple can be estimated by equation 1 : (1) the average or dc value of the inductor current equals the load current, or output current i out , in steady state. peak inductor current can be calculated by equation 2 i peak = i out + i lripple / 2 (2) valley inductor current can be calculated by equation 3 i valley = i out ? i lripple / 2 (3) in auto mode, the ccm to dcm boundary condition is when i valley = 0 a. when i lripple i peak_min , the load current at the dcm boundary condition can be found by equation 4 . when the peak-to-peak ripple current is smaller than i lripple i peak-min , the pfm boundary will be reached first. i out-dcm = i lripple / 2 when ? i lripple i peak_min (4) in auto mode, the pfm operation boundary condition is when i peak = i peak_min . frequency foldback occurs when peak current drops to i peak_min , no matter whether in ccm or dcm operation. when current ripple is small, i lripple < i peak_min , the peak current reaches i peak_min when still in ccm. the output current at ccm pfm boundary can be found by equation 5 i out-ccm-pfm = i peak-min ? i lripple / 2 when ? i lripple < i peak-min (5) the current ripple increases with reduced frequency if load reduces. when valley current reaches zero, the frequency continues to fold back with constant peak current and discontinuous current. in fpwm mode, there is no i peak-min limit. the peak current is defined by equation 2 at light loads and heavy loads. see frequency synchronization and mode setting for mode setting options in lm73605-q1/6-q1. mode setting only affects operation at light loads. there is no difference if load current is above the dcm and pfm boundary conditions discussed above. i l i l t t t i l ccm dcm pfm i l t i l t ccm auto mode fpwm mode i l t ccm ccm heavy loads light loads very light loads u u in out out lripple sw in (v v ) v i = f l v
14 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) 7.3.3 fixed-frequency peak current-mode control the lm73605-q1/6-q1 synchronous switched mode voltage regulator employs fixed frequency peak current mode control with advanced features. the fixed switching frequency is controlled by an internal clock. to get accurate dc load regulation, a voltage feedback loop is implemented to generate peak current command. the hs switch is turned on at the rising edge of the clock. as shown in figure 12 , during the hs switch on-time t on , the sw pin voltage v sw swings up to approximately v in , and the inductor current i l increases with a linear slope. the hs switch is turned off when the inductor current reaches the peak current command. during the hs switch off-time t off , the ls switch is turned on. inductor current discharges through the ls switch, which forces the v sw to swing below ground by the voltage drop across the ls switch. the ls switch is turned off at the next clock cycle, before the hs switch is turned on. the regulation loop adjusts the peak current command to maintain a constant output voltage. figure 12. sw voltage and inductor current waveforms in ccm duty cycle d is defined by the on-time of the hs switch over the switching period: d = t on / t sw where ? t sw = 1 / f sw is the switching period (6) in an ideal buck converter, where losses are ignored, d is proportional to the output voltage and inverse proportional to the input voltage: d = v out ? v in . when the lm73605-q1/6-q1 is set to operate in auto mode, the ls switch is turned off when its current reaches zero ampere before the next clock cycle comes. both hs switch and ls switch are off before the hs switch is turned on at the next clock cycle. 7.3.4 adjustable output voltage the voltage regulation loop in the lm73605-q1/6-q1 regulates the fb pin voltage to be the same as the internal reference voltage. the output voltage of the lm73605-q1/6-q1 is set by a resistor divider to program the ratio from v out to v fb . the resistor divider is connected from the output to ground with the mid-point connecting to the fb pin. figure 13. output voltage setting by resistor divider 0 0 v in -v d t on t t inductor current d = t on / t sw v sw t sw i l sw voltage i out i l-peak i lripple i l-valley t off fb r fbt r fbb vout
15 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) the internal voltage reference and feedback loop produce precise voltage regulation over temperature. ti recommends using divider resistors with 1% tolerance or better, and with temperature coefficient of 100 ppm or lower. typically, r fbt = 10 k ? to 100 k ? is recommended. larger r fbt and r fbb values reduce the quiescent current going through the divider, which help maintain high efficiency at very light load. but larger divider values also make the feedback path more susceptible to noise. if efficiency at very light load is critical in a certain application, r fbt up to 1 m ? can be used. r fbb can be calculated by equation 7 : (7) the minimum programmable v out equals v fb , with r fbb open. the maximum v out is limited by the maximum duty cycle at a given frequency: d max = 1 ? (t off-min / t sw ) where ? t off-min is the minimum off time of the hs switch ? t sw = 1 / f sw is the switching period (8) ideally, without frequency foldback, v out_max = v in_min d max . power losses in the circuit reduces the maximum output voltage. the lm73605-q1/6-q1 folds back switching frequency under t off_min condition to further extend v out_max . the device maintains output regulation with lower input voltage. the minimum fold-back frequency is limited by the maximum hs on-time, t on_max . maximum output voltage with frequency foldback can be estimated by: (9) the voltage drops on the hs mosfet and inductor dcr have been taken into account in equation 9 . the switching losses were not included. if the resistor divider is not connected properly, the output voltage cannot be regulated because the feedback loop cannot obtain correct output voltage information. if the fb pin is shorted to ground or disconnected, the output voltage is driven close to v in . the load connected to the output could be damaged under this condition. do not short fb to ground or leave it open circuit during operation. the fb pin is a noise sensitive node. it is important to place the resistor divider as close as possible to the fb pin, and route the feedback node with a short and thin trace. the trace connecting v out to r fbt can be long, but it must be routed away from the noisy area of the pcb. for more layout recommendations, see layout . 7.3.5 enable and uvlo the lm73605-q1/6-q1 regulates output voltage when the vcc voltage is higher than the undervoltage lock out (uvlo) level, v cc_uvlo , and the en voltage is higher than v en_vout_h . the internal ldo output voltage vcc is turned on when the en voltage is higher than v en_vcc_h . the precision enable circuitry is also turned on when vcc is above uvlo. normal operation of the lm73605-q1/6-q1 with regulated output voltage is enabled when the en voltage is greater than v en_vout_h . when the en voltage is less than v en_vcc_l , the device is in shutdown mode. the internal dividers make sure v en_vout_h is always higher than v en_vcc_h . the en pin cannot be left floating. the simplest way to enable the operation of the lm73605-q1/6-q1 is to connect the en pin to pvin, which allows self-start-up of the lm73605-q1/6-q1 when v in rises. use of a pullup resistor between pvin and en pins helps reduce noise coupling from pvin pin to the en pin. many applications benefit from employing an enable divider to establish a customized system uvlo. this can be used either for sequencing, system timing requirement, or to reduce the occurrence of deep discharge of a battery power source. figure 14 shows how to use a resistor divider to set a system uvlo level. an external logic output can also be used to drive the en pin for system sequencing. fb fbb fbt out fb v r r v v u u on _ max out _ max in_min out ds_on_hs on _ max off_min t v v i (r dcr) t t
16 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) figure 14. system uvlo with a selected r ent , the r enb can be calculated by: where ? v in_on_h is the desired supply voltage threshold to turn on this device (10) note that the divider adds to supply quiescent current by v in / (r ent + r enb ). small r ent and r enb values add more quiescent current loss. however, large divider values make the node more sensitive to noise. r ent in the hundreds of k range is a good starting point. 7.3.6 internal ldo, v cc_uvlo , and bias input the lm73605-q1/6-q1 integrates an internal ldo, generating vcc voltage for control circuitry and mosfet drivers. the vcc pin must have a 1- f to 4.7- f bypass capacitor placed as close as possible to the pin and properly grounded. do not load the vcc pin or short it to ground during operation. shorting vcc pin to ground during operation may damage the device. the uvlo on vcc voltage, v cc_uvlo , turns off the regulation when vcc voltage is too low. it prevents the lm73605-q1/6-q1 from operating until the vcc voltage is enough for the internal circuitry. hysteresis on v cc_uvlo prevents the part from turning off during power up if v in droops due to input current demands. the ldo generates vcc voltage from one of the two inputs: the supply voltage v in , or the bias input. when bias is tied to ground, the ldo input is v in . when bias is tied to a voltage higher than 3.3 v, the ldo input is v bias . bias voltage must be lower than both v in and 18 v. the bias input is designed to reduce the ldo power loss. the ldo power loss is: p loss_ldo = i ldo (v in_ldo ? v out_ldo ) (11) the higher the difference between the input and output voltages of the ldo, the more loss occurs to supply the same ldo output current. the bias input provides an option to supply the ldo with a lower voltage than v in , to reduce the difference of the input and output voltages of the ldo and reduce power loss. for example, if the ldo current is 10 ma at a certain frequency with v in = 24 v and v out = 5 v. the ldo loss with bias tied to ground is equal to 10 ma (24 v ? 3.27 v) = 207.3 mw, while the loss with bias tied to v out is equal to 10 ma (5 ? 3.27) = 17.3 mw. the efficiency improvement is more significant at light and mid loads because the ldo loss is a higher percentage in the total loss. the improvements is more significant with higher switching frequency because the ldo current is higher at higher switching frequency. the improvement is more significant when v in ? v out because the voltage difference is higher. figure 15 and figure 16 show efficiency improvement with bias tied to v out in a v out = 5 v and f sw = 2200 khz application, in auto mode and fpwm mode, respectively. vin enable r ent r enb en _ vout _ h enb ent in _ on _ h en_vout_h v r = r v v
17 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) v out = 5 v f sw = 2200 khz auto mode figure 15. lm73606-q1 efficiency comparison with bias = v out to bias = gnd in auto mode v out = 5 v f sw = 2200 khz fpwm mode figure 16. lm73606-q1 efficiency comparison with bias = v out to bias = gnd in fpwm mode ti recommends tying the bias pin to v out when v out is equal to or greater than 3.3 v and no greater than 18 v. tie the bias pin to ground when not in use. a ceramic capacitor, c bias , can be used from the bias pin to ground for bypassing. if v out has high frequency noise or spikes during transients or fault conditions, a resistor (1 to 10 ) connected between v out to bias can be used together with c bias for filtering. the vcc voltage is typically 3.27 v. when the lm73605-q1/6-q1 is operating in pfm mode with frequency foldback, vcc voltage is reduced to 3.1 v (typical) to further decrease the quiescent current and improve efficiency at very light loads. figure 17 shows an example of vcc voltage change with mode change. v out = 5 v f sw = 500 khz v in = 12 v figure 17. vcc voltage vs load current vcc voltage has an internal undervoltage lockout threshold, v cc_uvlo . when vcc voltage is higher than v cc_uvlo rising threshold, the device is active and in normal operation if v en > v en_vout_h . if vcc voltage droops below v cc_uvlo falling threshold, the v out is shut down. load current (a) vcc (v) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 vcc_ auto mode fpwm mode load current (a) efficiency (%) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 56 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 12 v bias = vout vin = 12 v bias = gnd vin = 24 v bias = vout vin = 24 v bias = gnd load current (a) efficiency (%) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 5 7 10 0 20 40 60 80 100 eff_ vin = 12 v bias = vout vin = 12 v bias = gnd vin = 24 v bias = vout vin = 24 v bias = gnd
18 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) 7.3.7 soft start and voltage tracking the lm73605-q1/6-q1 features controlled output voltage ramp during start-up. the soft-start feature reduces inrush current during start-up and improves system performance and reliability. if the ss/trk pin is floating, the lm73605-q1/6-q1 starts up following the fixed internal soft-start ramp. if longer soft-start time is desired, an external capacitor can be added from ss/trk pin to ground. there is a 2- a (typical) internal current source, i ssc , to charge the external capacitor. for a desired soft-start time t ss , capacitance of c ss can be found by equation 12 . c ss = i ssc t ss where ? c ss = soft-start capacitor value (f) ? i ssc = soft-start charging current (a) ? t ss = desired soft-start time (s) (12) the fb voltage always follows the lower potential of the internal voltage ramp or the voltage on the ss/trk pin. thus, the soft-start time can only be extended longer than the internal soft-start time by connecting c ss . use c ss to extend soft-start time when there are a large amount of output capacitors, or the output voltage is high, or the output is heavily loaded during start-up. lm73605-q1/6-q1 is operating in diode emulation mode during start-up regardless of mode setting. the device is capable of starting up into pre-biased output conditions. during start-up, the device sets the minimum inductor current to zero to avoid back charging the input capacitors. lm73605-q1/6-q1 can track an external voltage ramp applied to the ss/trk pin, if the ramp is slower than the internal soft-start ramp. the external ramp final voltage after start-up must be greater than 1.5 v to avoid noise interfering with the reference voltage. figure 18 shows how to use resistor divider to set v out to follow an external ramp. figure 18. soft start tracking external ramp v out tracking also provides the option of ramping up faster than the internal start-up ramp. the fb voltage always follows the lower potential of the internal voltage ramp and the voltage on the ss/trk pin. figure 19 shows the case when v out ramps slower than the internal ramp, while figure 20 shows when v out ramps faster than the internal ramp. if the tracking ramp is delayed after the internal ramp is completed, v fb follows the tracking ramp even if it is faster than the internal ramp. faster start-up time may result in large inductor current during start-up. use with special care. figure 19. tracking with longer start-up time than the internal ramp enable internal ss ramp ext tracking signal to ss pin v out ss/trk r trt r trb ext ramp
19 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) figure 20. tracking with shorter start-up time than the internal ramp the ss/trk pin is discharged to ground by an internal pulldown resistor r ssd when the output voltage is shutting down, such as in the event of uvlo, thermal shutdown, hiccup, or v en = 0. if a large c ss is used, and the time when v en = 0 v is very short, the c ss may not be fully discharged before the next soft start. under this condition, the fb voltage follows the internal ramp slew rate until the voltage on c ss is reached, then follow the slew rate defined by c ss . 7.3.8 adjustable switching frequency the internal oscillator frequency is controlled by the impedance on the rt pin. if the rt pin is open circuit, the lm73605-q1/6-q1 operates at its default switching frequency, 500 khz. the rt pin is not designed to be connected directly to ground. to program the switching frequency by r t resistor, equation 13 , or figure 21 , or table 1 can be used to find the resistance value. (13) figure 21. r t resistance vs switching frequency table 1. typical frequency setting resistance switching frequency f sw (khz) r t resistance (k ) 350 115 400 100 500 78.7 (or open) 750 52.3 1000 39.2 1500 26.1 2000 19.1 2200 17.4 enable internal ss ramp ext tracking signal to ss pin v out : u u t -5 sw 1 r (k ) = f (khz) 2.675 10 0.0007 frequency (khz) rt (k : ) 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 10 20 30 40 50 60 70 80 90 100 110 120 rt_f
20 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated the choice of switching frequency is usually a compromise between conversion efficiency and the size of the solution. lower switching frequency has lower switching losses (including gate charge losses, switch transition losses, etc.). it usually results in higher overall efficiency. however, higher switching frequency allows the use of smaller power inductor and output capacitors, hence a more compact design. lower inductance also helps transient response (higher large signal slew rate of inductor current), and has lower dcr. the optimal switching frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis. factors that need to be taken into account include input voltage range, output voltage, most frequent load current level(s), external component choices, solution size/cost requirements, efficiency and thermal management requirements. the choice of switching frequency may also be limited whether an operating condition triggers t on_min or t off-min . minimum on-time, t on-min , is the smallest time that the hs switch can be on. minimum off-time, t off-min , is the smallest duration that the hs switch can be off. in ccm operation, t on-min and t off_min limits the voltage conversion range given a selected switching frequency, f sw . the minimum duty cycle allowed is: d min = t on-min f sw (14) the maximum duty cycle allowed is: d max = 1 ? t off-min f sw (15) given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution size and efficiency. the maximum operational supply voltage can be found by: v in-max = v out / (f sw t on-min ) (16) at lower supply voltage, the switching frequency decreases once t off-min is tripped. the minimum v in without frequency foldback can be approximated by: v in-min = v out / (1 ? f sw t off-min ) (17) with a desired v out , the range of allowed v in is narrower with higher switching frequency. lm73605-q1/6-q1 has an advanced frequency fold-back algorithm under both t on_min and t off_min conditions. with frequency foldback, stable output voltage regulation is extended to wider range of supply voltages. at very high v in conditions, where t on_min limitation is met, the switching frequency reduces to allow higher v in while maintaining v out regulation. note that the peak to peak inductor current ripple will increase with higher v in and lower frequency. ti does not recommend designing the circuit to operate with t on_min under typical conditions. at very low v in conditions, where t off_min limitation is met, the switching frequency decreases until t on_max condition is met. such frequency fold-back mechanism allows the lm73605-q1/6-q1 to have very low dropout voltage regardless of frequency setting. 7.3.9 frequency synchronization and mode setting the lm73605-q1/6-q1 switching action can synchronize to an external clock from 350 khz to 2.2 mhz. ti recommends connecting the external clock to the sync/mode pin with an appropriate termination resistor. ground the sync/mode pin if not used. figure 22. frequency synchronization recommendations for the external clock include a high level no lower than 2 v, low level no higher than 0.4 v, duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. when the external clock fails at logic high or low, the lm73605-q1/6-q1 switches at the frequency programmed by the r t resistor after a time-out period. ti recommends connecting a resistor to the rt pin such that the internal oscillator frequency is the same as the external clock frequency. this allows the regulator to continue operating at approximately the same switching frequency if the external clock fails with the same control loop behavior. sync/ mode r sync ext clock
21 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated the sync/mode pin is also used as an operation mode control input. ? to set the operation in auto mode, connect sync/mode pin to ground, or a logic signal lower than 0.3 v. ? to set the operation in fpwm mode, connect sync/mode pin to a bias voltage or logic signal greater than 0.6 v. ? when the lm73605-q1/6-q1 is synchronized to an external clock, the operation mode is fpwm. table 2 summarizes the operation mode and features according to the sync/mode input signal. for more details, see active mode and auto mode and fpwm mode . table 2. sync/mode pin settings and operation modes sync/mode input switching frequency operating mode light load behavior logic low set by r t resistor auto mode ? no negative inductor current, device operates in discontinuous conduction mode (dcm) when current valley reaches 0 a. ? minimum peak inductor current is limited at i peak_min ; device operates in pulse frequency modulation (pfm) mode when peak current reaches i peak_min . ? switching frequency reduces in pfm mode. logic high set by r t resistor fpwm mode ? fixed frequency continuous conduction mode (ccm) regardless of load ? inductor current have negative portion at light loads ? no i peak_min external clock set by external clock 7.3.10 internal compensation and c ff the lm73605-q1/6-q1 is internally compensated. the internal compensation is designed such that the loop response is stable over a wide operating frequency and output voltage range. the internal r-c values are 500 k ? and 30 pf respectively. when large resistance value (m ) is used for r fbt , the pole formed by an internal parasitic capacitor and r fbt can be low enough to reduce the phase margin. if only low esr output capacitors (ceramic types) are used for c out , the control loop could have low phase margin. to provide a phase boost an external feed-forward capacitor (c ff ) can be added in parallel with r fbt . choose the c ff capacitor to provide most phase boost at the estimated crossover frequency f x : where ? k = 20.27 with lm73605 -q1 ? k = 24.16 with lm73606 -q1 (18) select c out so that the f x is no higher than 1/6 of the switching frequency. typically, f x / f sw = 1/10 to 1/8 provides a good combination of stability and performance. place the external feed-forward capacitor in parallel with the top resistor divider r fbt when additional phase boost is needed. figure 23. feed-forward capacitor for loop compensation the feed-forward capacitor c ff in parallel with r fbt places an additional zero before the crossover frequency of the control loop to boost phase margin. the zero frequency can be found by equation 19 : f z-cff = 1 / (2 r fbt c ff ) (19) an additional pole is also introduced with c ff at the frequency of: f p-cff = 1 / (2 c ff (r fbt // r fbb )) (20) u x out out k f = v c fb r fbt r fbb c ff vout
22 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated select the c ff so that the bandwidth of the control loop without the c ff is centered between f z-cff and f p-cff . the zero at f z-cff adds phase boost at the crossover frequency and improves transient response. the pole at f p-cff helps maintaining proper gain margin at frequency beyond the crossover. the need of c ff depends on r fbt and c out . typically, choose r fbt 100 k . c ff may not be required, because the internal parasitic pole is at higher frequency. if c out has larger esr, and esr zero f z-esr = 1 / (2 esr c out ) is low enough to provide phase boost around the crossover frequency, do not use c ff . equation 21 was tested for ceramic output capacitors: (21) the c ff creates a time constant with r fbt that couples in the attenuated output voltage ripple to the fb node. if the c ff value is too large, it can couple too much ripple to the fb and affect v out regulation. it could also couple too much transient voltage deviation and falsely trigger pgood flag. 7.3.11 bootstrap capacitor and v boot-uvlo the driver of the hs switch requires a bias voltage higher than the v in voltage. the capacitor, c boot in simplified schematic , connected between cboot and sw pins works as a charge pump to boost voltage on the cboot pin to (v sw + v cc ). a boot diode is integrated on the die to minimize external component count. ti recommends a high-quality 0.47- f, 6.3-v or higher voltage ceramic capacitor for c boot . the v boot_uvlo threshold is designed to maintain proper hs switch operation. if the c boot is not charged above this voltage with respect to sw, the device initiates a charging sequence using the ls switch before turning on the hs switch. 7.3.12 power-good and overvoltage protection the lm73605-q1/6-q1 has a built-in power-good (pgood) flag to indicate whether the output voltage is at an appropriate level or not. the pgood flag can be used for start-up sequencing of multiple rails. the pgood pin is an open-drain output that requires a pullup resistor to an appropriate logic voltage (any voltage below 15 v). the pin can sink 5 ma of current and maintain its specified logic low level. a typical pullup resistor value is 10 k ? to 100 k ? . when the fb voltage is higher than v pgood-ov or lower than v pgood-uv threshold, the pgood internal switch is turned on, and the pgood pin voltage is pulled low. when the fb is within the range, the pgood switch is turned off, and the pin is pulled up to the voltage connected to the pullup resistor. the pgood function also have a deglitch timer for about 140 s for each transition. if it is desired to pull up pgood pin to a voltage higher than 15 v, a resistor divider can be used to divide the voltage down. figure 24. divider for pgood pullup voltage with a given pullup voltage v pu , select a desired voltage on the pgood pin, v pg . with a selected r pgt , the r pgb can be found by: (22) when the device is disabled, the output voltage is low, and the pgood flag indicates logic low as long as v in > 2 v. pg pgb pgt pu pg v r = r v v v pu r pgt r pgb pgood ff x fbt fbt fbb 1 1 c = 2 f r (r // r ) u u s u u
23 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3.13 overcurrent and short-circuit protection the lm73605-q1/6-q1 is protected from overcurrent conditions with cycle-by-cycle current limiting on both hs and ls mosfets. the hs switch is turned off when hs current goes beyond the peak current limit, i hs-limit . the ls switch can only be turned off when ls current is below ls current limit, i ls-limit . if the ls switch current is higher than i ls-limit at the end of a switching cycle, the switching cycle is extended until the ls current reduces below the limit. current limiting on both hs and ls switches provides tighter control of the maximum dc inductor current, or output current. they also help prevent runaway current at extreme conditions. with lm73605-q1/6-q1, the maximum output current is always limited at i dc_limit = (i hs_limit + i ls_limit ) / 2 (23) the lm73605-q1/6-q1 employs hiccup current protection at extreme overload conditions, including short-circuit condition. hiccup is only activated when v out droops below 40% (typical) of the regulation voltage and stays below for 128 consecutive switching cycles. under overcurrent conditions when v out has not fallen below 40% of regulation, the lm73605-q1/6-q1 continues operation with cycle-by-cycle hs and ls current limiting. hiccup is disabled during soft-start. when hiccup is triggered, the device turns off v out regulation and re-tries soft start after a re-try delay time, t oc = 46 ms (typical). the long wait time allows the device, and the load, to cool down under such fault conditions. if the fault condition still exists when re-try, hiccup shuts down the device and repeats the wait and re-try cycle. if the fault condition has been removed, the device starts up normally. if tracking was used for initial sequencing, the device restarts using the internal soft-start ramp. hiccup mode helps to reduce the device power dissipation and die temperature under severe overcurrent conditions and short circuits. it improves system reliability and prolongs the life span of the device. in fpwm mode, negative current protection is implemented to protect the switches from extreme negative currents. when ls switch current reaches i neg-limit , ls switch turns off, and hs switch turns on to conduct the negative current. hs switch is turned off once its current reaches 0 a. 7.3.14 thermal shutdown thermal shutdown protection prevents the device from extreme junction temperature. the device is turned off when the junction temperature exceeds 160 c (typical). after thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature drops to approximately 135 c. when the junction temperature falls below 135 c, the lm73605-q1/6-q1 restarts.
24 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.4 device functional modes 7.4.1 shutdown mode the en pin provides electrical on/off control of the device. when the en pin voltage is below v en_vcc_l , the device is in shutdown mode. the ldo output voltage v cc = 0 v and the output voltage v out = 0 v. in shutdown mode the quiescent current drops to a very low value. 7.4.2 standby mode the internal ldo has a lower en threshold than that required to start the regulator. when the en pin voltage is above v en_vcc_h , the internal ldo regulates the vcc voltage. the precision enable circuitry is turned on once v cc is above v cc_uvlo . the device is in standby mode if en voltage is below v en_vout_h . the internal mosfets remains in tri-state unless the voltage on en pin goes beyond v en_vout_h threshold. the lm73605-q1/6-q1 also employs uvlo protection. if the vcc voltage is below the v cc_uvlo level, the output of the regulator is turned off. 7.4.3 active mode the lm73605-q1/6-q1 is in active mode when the en voltage is above v en_vout_h , and v cc is above v cc_uvlo . the simplest way to enable the operation of the lm73605-q1/6-q1 is to pull up the en pin to pvin, which allows self-start-up when the input voltage ramps up. in active mode, depending on the load current and mode setting, the lm73605-q1/6-q1 is in one of four modes: 1. ccm with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple; 2. dcm with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current ripple in ccm operation; 3. pfm when switching frequency is decreased at very light load; 4. under overcurrent or overtemperature conditions, the device operates in one of the fault protection modes. see table 2 for mode-setting details. 7.4.3.1 ccm mode in ccm operation, inductor current has a continuous triangular waveform. the hs switch is on at the beginning of a switching cycle and the ls switch is turned off the end of each switching cycle. in auto mode, the lm73605- q1/6-q1 operates in ccm when the load current is higher than ? of the peak-to-peak inductor current (i lripple ). in fpwm mode, the lm73605-q1/6-q1 operates in ccm regardless of load. in ccm operation, the switching frequency is typically constant, unless t on-min , t off-min , or i peak-min conditions are met. the constant switching frequency is determined by rt pin setting, or the external synchronization clock frequency. the duty cycle is also constant in ccm: d = v out / v in if loss is ignored, regardless of load. the peak-to-peak inductor ripple is constant with the same v in and v out , regardless of load. with very high or very low supply voltages, when the t on-min or t off-min condition is met, the frequency reduces to maintain v out regulation with even higher or lower v in , respectively. when the i peak_min condition is met in auto mode, switching frequency will fold back to provide higher efficiency. i peak_min is disabled in fpwm mode. 7.4.3.2 dcm mode dcm operation only happens in auto mode, when the load current is lower than half of the ccm inductor current ripple, and peak current is higher than i peak-min . there is no dcm in fpwm mode. dcm is also known as diode emulation mode. the ls fet is turned off when the inductor current ramps to 0 a. dcm has the same switching frequency as ccm, which is set by the rt pin. duty cycle and peak current reduces with lighter load in dcm. dcm is more efficient than fpwm under the same condition, because of lower switching losses and lower conduction losses. when the peak current reduces to i peak_min at lighter load, the lm73605-q1/6-q1 operates in pfm mode.
25 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) 7.4.3.3 pfm mode pulse-frequency-modulation (pfm) mode is activated when peak current is lower than i peak-min , only in auto mode. peak current is kept constant and v out is regulated by frequency. efficiency is greatly improved by lowered switching losses, especially at very light loads. in pfm operation, a small dc positive offset appears on v out . the lower the frequency is folded back in pfm, the more the dc offset is on v out . see v out regulation curves in application curves . if the dc offset on v out is not acceptable, a dummy load at v out , or lower r fbt and r fbb resistance values can be used to reduce the offset. alternatively the device can be run in fpwm mode where the switching frequency is constant, and no offset is added to affect the v out accuracy unless t on_min is reached. 7.4.3.4 fault protection mode the lm73605-q1/6-q1 has hiccup current protection at extreme overload and short circuit conditions. hiccup is activated when v out droops below 40% (typical) of the regulation voltage and stays for 128 consecutive switching cycles. hiccup is disabled during soft start. in hiccup, the device turns off v out and re-tries soft start after 46-ms wait time. cycle repeats until overcurrent fault condition has been removed. hiccup mode helps to reduce the device power dissipation and die temperature under severe overcurrent conditions and short circuits. it improves system reliability and prolongs the life span of the device. under overcurrent conditions when v out droops below regulation but above 40% of regulated voltage, the lm73605-q1/6-q1 stays in cycle-by-cycle hs and ls current limiting protection mode. thermal shutdown prevents the device from extreme junction temperature by turning off the device when the junction temperature exceeds 160 c (typical). after thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature drops to approximately 135 c. when the junction temperature falls below 135 c, the lm73605-q1/6-q1 restarts.
26 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the lm73605-q1/6-q1 device is a step-down dc-dc voltage regulator. it is designed to operate with a wide supply voltage range (3.5 v to 36 v), wide switching frequency range (350 khz to 2.2 mhz), and wide output voltage range: up to 95% v in . lm73605-q1/6-q1 is a synchronous converter with both hs and ls mosfets integrated, and it is capable of delivering a maximum output current of 5 a (lm73605 -q1) or 6 a (lm73606 -q1). the following design procedure can be used to select component values for the lm73605-q1/6-q1. alternately, the webench ? software may be used to generate a complete design. the webench ? software uses an iterative design procedure and accesses a comprehensive database of components when generating a design (see custom design with webench ? tools ). this section presents a simplified discussion of the design process. 8.2 typical application the lm73605-q1/6-q1 only requires a few external components to perform high-efficiency power conversion, as shown in simplified schematic . figure 25. lm73605-q1/6-q1 basic schematic the lm73605-q1/6-q1 also integrates many practical features to meet a wide range of system design requirements and optimization, such as uvlo, programmable soft-start time, start-up tracking, programmable switching frequency, clock synchronization and a power-good flag. note that for ease of use, the feature pins do not require an additional component when not in use. they can be either left floating or shorted to ground. please refer to pin configuration and functions for details. a comprehensive schematic with all features utilized is shown in figure 26 . sw pvin pgnd cboot vcc bias en agnd fb v in c out c boot c in c vcc v out r fbt r fbb l sync/ mode rt ss/trk pgood copyright ? 2017, texas instruments incorporated
27 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical application (continued) (1) all the c out values are after derating. add more when using ceramics. figure 26. lm73605-q1/6-q1 comprehensive schematic with all features utilized the external components must fulfill not only the needs of the power conversion, but also the stability criteria of the control loop. the lm73605-q1/6-q1 is optimized to work with a range of external components. for quick component selection, table 3 can be used. table 3. typical component selection f sw (khz) v out (v) l ( h) c out ( f) (1) r fbt (k ) r fbb (k ) r t (k ) 350 1 2.2 500 100 open 115 500 1 1.5 400 100 open 78.7 or open 1000 1 0.68 200 100 open 39.2 2200 1 0.47 100 100 open 17.4 350 3.3 4.7 200 100 43.5 115 500 3.3 3.3 150 100 43.5 78.7 or open 1000 3.3 1.8 88 100 43.5 39.2 2200 3.3 1.2 44 100 43.5 17.4 350 5 6.8 120 100 25 115 500 5 4.7 88 100 25 78.7 or open 1000 5 3.3 66 100 25 39.2 2200 5 2.2 44 100 25 17.4 350 12 15 66 100 9.1 115 500 12 10 44 100 9.1 78.7 or open 1000 12 6.8 22 100 9.1 39.2 350 24 22 40 100 4.3 115 500 24 15 30 100 4.3 78.7 or open copyright ? 2017, texas instruments incorporated c ss r t r sync r ent r enb sw pvin pgnd cboot vcc bias en agnd fb v in c out c boot c in c vcc v out r fbt r fbb l sync/ mode rt ss/trk pgood
28 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2.1 design requirements detailed design procedure is described based on a design example. for this design example, use the parameters listed in table 4 . table 4. design example parameters design parameter value typical input voltage 12 v output voltage 5 v output current 5 a operating frequency 500 khz soft-start time 11 ms 8.2.2 detailed design procedure 8.2.2.1 custom design with webench ? tools to create a custom design with the webench ? power designer, click the lm73605-q1 or lm73606-q1 device. 1. start by entering the input voltage (v in ), output voltage (v out ), and output current (i out ) requirements. 2. optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. compare the generated design with other possible solutions from texas instruments. the webench power designer provides a customized schematic along with a list of materials with real-time pricing and component availability. in most cases, these actions are available: ? run electrical simulations to see important waveforms and circuit performance ? run thermal simulations to understand board thermal performance ? export customized schematic and layout into popular cad formats ? print pdf reports for the design, and share the design with colleagues get more information about webench tools at www.ti.com/webench . 8.2.2.2 output voltage setpoint the output voltage of the lm73605-q1/6-q1 device is externally adjustable using a resistor divider network. the divider network is comprised of top feedback resistor r fbt and bottom feedback resistor r fbb . use equation 24 to determine the output voltage of the converter. (24) typically, r fbt = 10 k ? to 100 k ? is recommended. larger r fbt and r fbb values reduce the quiescent current going through the divider, which help maintain high efficiency at very light loads. but larger divider values also make the feedback path more susceptible to noise. if efficiency at very light loads is critical in a certain application, r fbt up to 1 m ? can be used. (25) r fbt = 100 k is selected here. r fbb = 24.99 k can be calculated to get 5-v output voltage. 8.2.2.3 switching frequency the default switching frequency of the lm73605-q1/6-q1 device is set at 500 khz. for this design, the rt pin can be floating, and the lm73605-q1/6-q1 switches at 500 khz in ccm mode. an r t resistor of 78.7 k , calculated using equation 13 , figure 21 , or table 1 , can be connected from rt pin to ground to obtain 500-khz operation frequency as well. fbt out fb fbb r v = v 1 + r u ? ? 1 fb fbb fbt out fb v r r v v
29 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated the lm73605-q1/6-q1 switching action can synchronize to an external clock from 350 khz to 2.2 mhz. ti recommends connecting an external clock to the sync/mode pin with a 50- to 100- ? termination resistor. the sync/mode pin must be grounded if not used. rt pin is floating and sync/mode pin is tied to ground in this design. 8.2.2.4 input capacitors the lm73605-q1/6-q1 device requires high-frequency ceramic input decoupling capacitors. depending on the application, a bulk input capacitor can also be added. the typical recommended ceramic decoupling capacitors include one small, 0.1 f to 1 f, and one large, 10 f to 22 f, capacitors. ti recommends high-quality ceramic type x5r or x7r capacitors. the voltage rating must be greater than the maximum input voltage. as a general rule, to compensate the derating ti recommends a voltage rating of twice the maximum input voltage. it is very important in buck regulator to place the small decoupling capacitor right next to the pvin and pgnd pins. this capacitor is used to bypass the high frequency switching noise by providing a return path of the noise. it prevents the noise from spreading to wider area of the board. the large bypass ceramic capacitor must also be as close as possible to the pvin and pgnd pins. additionally, some bulk capacitance may be required, especially if the lm73605-q1/6-q1 circuit is not located within approximately 2 inches from the input voltage source. this capacitor is used to provide damping to the voltage spike due to the lead inductance of the cable. the optimum value for this capacitor is four times the ceramic input capacitance with esr close to the characteristic impedance of the lc filter formed by your input inductance and your ceramic input capacitors. it is not critical that the electrolytic filter be at the optimum value for damping, but it must be rated to handle the maximum input voltage including ripple voltage. for this design, two 10- f, x7r dielectric capacitors rated for 50 v are used for the input decoupling capacitance, and a capacitor with a value of 0.47 f for high-frequency filtering. note dc bias effect: high capacitance ceramic capacitors have a dc bias derating effect, which will have a strong influence on the final effective capacitance. therefore, the right capacitor value has to be chosen carefully. package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance. 8.2.2.5 inductor selection the first criterion for selecting an output inductor is the inductance. in most buck converters, this value is based on the desired peak-to-peak ripple current in the inductor, i lripple . an inductance that gives a ripple current of 10% to 30% of the maximum output current (5 a or 6 a) is a good starting point. the inductance can be calculated from equation 26 : where ? i lripple = (0.1 to 0.3) i l_max ? i l_max = 5 a for lm73605-q1 and 6 a for lm73606-q1 ? d = v out / v in (26) selected i lripple is between 10% to 30% of the rated current of the device. as with switching frequency, the selection of the inductor is a tradeoff between size, cost, and performance. higher inductance gives lower ripple current and hence lower output voltage ripple. with peak current mode control, the current ripple is the input signal to the control loop. a certain amount of ripple current is needed to maintain the signal-to-noise ratio of the control loop. within the same series (same size/height), a larger inductance will have a higher series resistance (esr). with similar esr, size and/or height will be greater. larger inductance also has slower current slew rate during large load transients. in out sw lripple | v v d l i u u
30 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated lower inductance usually results in a smaller, less expensive component; however, the current ripple will be higher, thus more output capacitor is needed to maintain the same amount of output voltage ripple. the rms current is higher with the same load current due to larger ripple. the switching loss is higher because the switch current, which is the peak current, is higher when the hs switch turns off and ls switch turns on. core loss of the inductor is also larger with higher ripple. core loss needs to be considered, especially with higher switching frequencies. check the ripple current over v in_min to v in_max range to make sure current ripple is reasonable over entire supply voltage range. for applications with large v out and typical v out / v in > 50%, sub-harmonic oscillation can be a concern in peak current-mode-controlled buck converters. select inductance so that l v out / (n f sw ) where ? n = 3 with lm73605-q1 ? n = 3.6 with lm73606-q1 (27) the second criterion is inductor saturation current rating. because the maximum inductor current is limited by the high-side switch current limit, it is advised to select an inductor with a saturation current higher than the i limit-hs . ti recommends selection of soft saturation inductors. a power inductor could be the major source of radiated noise. when emi is a concern in the application, select a shielded inductor, if possible. for this design, 20% ripple of 5 a yields 5.8- h inductance. a 4.7- h inductor is selected, which gives 25% ripple current. 8.2.2.6 output capacitor selection the output capacitor is responsible for filtering the inductor current, and supplying load current during transients. capacitor selection depends on application conditions as well as ripple and transient requirements. best performance is achieved by using ceramic capacitors or combinations of ceramic and other types of capacitors. for high output voltage conditions, such as 12 v and above, finding ceramic capacitors that are rated for an appropriate voltage becomes challenging. in such cases choose a low-esr sp-cap ? or poscap ? -type capacitor. it is a good idea to use a low-value ceramic capacitor in parallel with other capacitors, to bypass high frequency noise between ground and v out . for a given input and output requirement, equation 28 gives an approximation for a minimum output capacitor required. where ? r = ripple ratio of the inductor ripple current (i lripple / 5 a or 6 a) ? v out = target output voltage undershoot, for example, 5% to 10% of v out ? d ? = 1 ? duty cycle ? f sw = switching frequency ? i out = load current (28) along with equation 28 , for the same requirement calculate the maximum esr with equation 29 . (29) the output capacitor is also the dominating factor in the loop response of a peak-current mode controlled buck converter. a simplified estimation of the control loop crossover frequency can be found by equation 18 . select c out so that the f x is no higher than 1/6 of the switching frequency. typically, f x / f sw = 1/10 to 1/8 provides a good combination of stability and performance. for this design, one 0.47- f, 50-v x7r and four 22- f, 16-v, x7r ceramic capacitors are used in parallel. c u u sw out d 1 esr ( 0.5) f c r a o c c ! u u u ? ? ? ? u u ' ? ? ? 1 ? ? 2 out sw out out 1 r c (1 d ) d (1 r) (f r v / i ) 12
31 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2.2.7 feed-forward capacitor the lm73605-q1/6-q1 is internally compensated. typically, select r fbt 100 k , then c ff is not needed. when very low quiescent current is needed, r fbt = 1 m may be used. if c out is mainly ceramic type low esr capacitors, an external feed-forward capacitor c ff may be needed to improve the phase margin. add c ff in parallel with r fbt . c ff is chosen such that the phase boost is maximized at the estimated crossover frequency f x . equation 21 was tested. with this design, because r fbt = 100 k is selected, no c ff is needed. 8.2.2.8 bootstrap capacitors every lm73605-q1/6-q1 design requires a bootstrap capacitor, c boot . the recommended bootstrap capacitor is 0.47 f and rated at 6.3 v or greater. the bootstrap capacitor is located between the sw pin and the cboot pin. the bootstrap capacitor must be a high-quality ceramic type with x7r or x5r grade dielectric for temperature stability. 8.2.2.9 vcc capacitor the vcc pin is the output of an internal ldo for lm73605-q1/6-q1. the input for this ldo comes from either v in or bias pin voltage. the recommended c vcc capacitor is 2.2 f and rated at 6.3 v or greater. it must be a high-quality ceramic type with x7r or x5r grade to insure stability. never short vcc pin to ground during operation. 8.2.2.10 bias because v out = 5 v in this design, the bias pin is tied to v out to reduce ldo power loss. the output voltage is supplying the ldo current instead of the input voltage. the power saving is i ldo (v in ? v out ). the power saving is more significant when v in > > v out and with higher frequency operation. to prevent v out noise and transients from coupling to bias, a series resistor, 1 to 10 , may be added between v out and bias. a bypass capacitor with a value of 1 f or higher can be added close to the bias pin to filter noise. 8.2.2.11 soft start the ss/trk pin can be floating to start up following the internal soft-start ramp. in order to extend the soft-start time, an external soft-start capacitor can be used. use equation 12 in order to calculate the soft-start capacitor value. with a desired soft-start time t ss = 11 ms, a soft-start charging current of i ssc = 2 a (typical), and v fb = 1.006 v (typical), equation 12 yields a soft-start capacitor value of 22 nf. 8.2.2.12 undervoltage lockout setpoint the system undervoltage lockout (uvlo) is adjusted using the external voltage divider network of r ent and r enb . with one selected r ent value, r enb can be found by equation 10 . note that the divider adds to supply quiescent current by v in / (r ent + r enb ). small r ent and r enb values add more quiescent current loss. however, large divider values make the node more sensitive to noise. in this design, en pin is tied to pvin pin with a 100-k resistor. 8.2.2.13 pgood for this design, a 100-k resistor is used to pull up pgood to v out .
32 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2.3 application curves v out = 3.3 v f sw = 400 khz auto mode figure 27. lm73606-q1 efficiency v out = 3.3 v f sw = 400 khz fpwm mode figure 28. lm73606-q1 efficiency v out = 3.3 v f sw = 500 khz auto mode figure 29. lm73605-q1 efficiency v out = 3.3 v f sw = 500 khz fpwm mode figure 30. lm73605-q1 efficiency v out = 3.3 v f sw = 2200 khz auto mode figure 31. lm73605-q1 efficiency v out = 3.3 v f sw = 2200 khz fpwm mode figure 32. lm73605-q1 efficiency load current (a) y axis title (unit) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 56 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 5 v vin = 8 v vin = 12 v vin = 13.5 v vin = 18 v load current (a) efficiency (%) 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 5 v vin = 8 v vin = 12 v vin = 13.5 v vin = 18 v load current (a) efficiency (%) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 5 v vin = 8v vin = 12 v load current (a) efficiency (%) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 5 v vin = 8v vin = 12 v load current (a) efficiency (%) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 5 v vin = 8v vin = 12 v load current (a) efficiency (%) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 5 v vin = 8v vin = 12 v
33 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated v out = 3.3 v f sw = 350 khz auto mode figure 33. lm73605-q1 efficiency v out = 3.3 v f sw = 1000 khz auto mode figure 34. lm73605-q1 efficiency v out = 5 v f sw = 400 khz auto mode figure 35. lm73606-q1 efficiency v out = 5 v f sw = 400 khz fpwm mode figure 36. lm73606-q1 efficiency v out = 5 v f sw = 500 khz auto mode figure 37. lm73606-q1 efficiency v out = 5 v f sw = 500 khz fpwm mode figure 38. lm73606-q1 efficiency load current (a) efficiency (%) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 56 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 7 v vin = 12 v vin = 24 v vin = 36 v load current (a) efficiency (%) 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 7 v vin = 12 v vin = 24 v vin = 36 v load current (a) efficiency (%) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 5 v vin = 8v vin = 12 v load current (a) efficiency (%) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 5 v vin = 8v vin = 12 v load current (a) efficiency (%) 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 8 v vin = 12 v vin = 13.5 v vin = 18 v load current (a) efficiency (%) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 56 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 8 v vin = 12 v vin = 13.5 v vin = 18 v
34 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated v out = 5 v f sw = 1000 khz auto mode figure 39. lm73606 -q1 efficiency v out = 5 v f sw = 1000 khz fpwm mode figure 40. lm73606-q1 efficiency v out = 5 v f sw = 2200 khz auto mode figure 41. lm73606-q1 efficiency v out = 5 v f sw = 2200 khz fpwm mode figure 42. lm73606-q1 efficiency v out = 12 v f sw = 500 khz auto mode figure 43. lm73605-q1 efficiency v out = 12 v f sw = 500 khz fpwm mode figure 44. lm73605-q1 efficiency load current (a) efficiency (%) 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 7 v vin = 12 v vin = 24 v load current (a) efficiency (%) 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 7 v vin = 12 v vin = 24 v load current (a) efficiency (%) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 56 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 7 v vin = 12 v vin = 24 v load current (a) efficiency (%) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 14 v vin = 24v vin = 36 v load current (a) efficiency (%) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 56 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 7 v vin = 12 v vin = 24 v load current (a) efficiency (%) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 50 55 60 65 70 75 80 85 90 95 100 eff_ vin = 14 v vin = 24v vin = 36 v
35 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated v out = 5 v f sw = 400 khz auto mode figure 45. lm73606-q1 load and line regulation v out = 5 v f sw = 400 khz fpwm mode figure 46. lm73606-q1 load and line regulation v out = 5 v f sw = 500 khz auto mode figure 47. lm73606-q1 load and line regulation v out = 5 v f sw = 500 khz fpwm mode figure 48. lm73606-q1 load and line regulation v out = 5 v f sw = 2200 khz auto mode figure 49. lm73605-q1 load and line regulation v out = 5 v f sw = 2200 khz fpwm mode figure 50. lm73605-q1 load and line regulation load current (a) output voltage (v) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 4.8 4.84 4.88 4.92 4.96 5 5.04 5.08 5.12 5.16 5.2 reg_ vin = 7 v vin = 12 v vin = 24 v load current (a) output voltage (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 4.95 4.96 4.97 4.98 4.99 5 5.01 5.02 5.03 5.04 5.05 reg_ vin = 7 v vin = 12 v vin = 24 v load current (a) output voltage (v) 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 4.9 4.92 4.94 4.96 4.98 5 5.02 5.04 5.06 5.08 5.1 reg_ vin = 7 v vin = 12 v vin = 24 v vin = 36 v load current (a) output voltage (v) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 5 7 10 4.8 4.84 4.88 4.92 4.96 5 5.04 5.08 5.12 5.16 5.2 reg_ vin = 7 v vin = 12 v vin = 24 v vin = 36 v load current (a) output voltage (v) 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 4.95 4.96 4.97 4.98 4.99 5 5.01 5.02 5.03 5.04 5.05 reg_ vin = 8 v vin = 12 v vin = 13.5 v vin = 18 v load current (a) output voltage (v) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 56 4.8 4.84 4.88 4.92 4.96 5 5.04 5.08 5.12 5.16 5.2 reg_ vin = 8 v vin = 12 v vin = 13.5 v vin = 18 v
36 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated v out = 3.3 v f sw = 400 khz auto mode figure 51. lm73606-q1 load and line regulation v out = 3.3 v f sw = 400 khz fpwm mode figure 52. lm73606-q1 load and line regulation v out = 3.3 v f sw = 2200 khz auto mode figure 53. lm73605-q1 load and line regulation v out = 3.3 v f sw = 2200 khz fpwm mode figure 54. lm73605-q1 load and line regulation v out = 3.3 v f sw = 500 khz auto mode figure 55. lm73605-q1 load and line regulation v out = 3.3 v f sw = 1000 khz auto mode figure 56. lm73605-q1 load and line regulation load current (a) output voltage (v) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 3.2 3.22 3.24 3.26 3.28 3.3 3.32 3.34 3.36 3.38 3.4 reg_ vin = 5 v vin = 8v vin = 12 v load current (a) output voltage (v) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 3.2 3.22 3.24 3.26 3.28 3.3 3.32 3.34 3.36 3.38 3.4 reg_ vin = 5 v vin = 8v vin = 12 v load current (a) output voltage (v) 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 3.25 3.26 3.27 3.28 3.29 3.3 3.31 3.32 3.33 3.34 3.35 reg_ vin = 5 v vin = 8 v vin = 12 v vin = 13.5 v vin = 18 v load current (a) output voltage (v) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 56 3.2 3.22 3.24 3.26 3.28 3.3 3.32 3.34 3.36 3.38 3.4 reg_ vin = 5 v vin = 8 v vin = 12 v vin = 13.5 v vin = 18 v load current (a) output voltage (v) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 3.27 3.275 3.28 3.285 3.29 3.295 3.3 3.305 3.31 3.315 3.32 reg_ vin = 5 v vin = 8v vin = 12 v load current (a) output voltage (v) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 3.2 3.22 3.24 3.26 3.28 3.3 3.32 3.34 3.36 3.38 3.4 reg_ vin = 5 v vin = 8v vin = 12 v
37 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated v out = 12 v f sw = 500 khz auto mode figure 57. lm73605-q1 load and line regulation v out = 12 v f sw = 500 khz fpwm mode figure 58. lm73605-q1 load and line regulation v out = 5 v f sw = 400 khz auto mode figure 59. lm73606-q1 dropout curve v out = 5 v f sw = 400 khz fpwm mode figure 60. lm73606-q1 dropout curve v out = 5 v f sw = 2200 khz auto mode figure 61. lm73605-q1 dropout curve v out = 5 v f sw = 2200 khz fpwm mode figure 62. lm73605-q1 dropout curve vin (v) output voltage (v) 4 4.4 4.8 5.2 5.6 6 6.4 6.8 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 do_5 load = 1.5ma load = 1a load = 3a load = 5a vin (v) output voltage (v) 4 4.4 4.8 5.2 5.6 6 6.4 6.8 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 do_5 load = 1.5 ma load = 1.5 a load = 3 a load = 6 a vin (v) output voltage (v) 4 4.4 4.8 5.2 5.6 6 6.4 6.8 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 do_5 load = 1.5ma load = 1a load = 3a load = 5a load current (a) output voltage (v) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 11.8 11.84 11.88 11.92 11.96 12 12.04 12.08 12.12 12.16 12.2 12.24 12.28 12.32 12.36 12.4 reg_ vin = 14 v vin = 24v vin = 36 v vin (v) output voltage (v) 4 4.4 4.8 5.2 5.6 6 6.4 6.8 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 do_5 load = 1.5 ma load = 1.5 a load = 3 a load = 6 a load current (a) output voltage (v) 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 4 55 11.9 11.92 11.94 11.96 11.98 12 12.02 12.04 12.06 12.08 12.1 reg_ vin = 14 v vin = 24v vin = 36 v
38 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated v out = 5 v f sw = 500 khz auto mode figure 63. lm73605-q1 dropout curve v out = 5 v f sw = 1000 khz auto mode figure 64. lm73605-q1 dropout curve v out = 3.3 v f sw = 400 khz auto mode figure 65. lm73606-q1 dropout curve v out = 3.3 v f sw = 400 khz fpwm mode figure 66. lm73606-q1 dropout curve v out = 3.3 v f sw = 500 khz auto mode figure 67. lm73605-q1 dropout curve v out = 12 v f sw = 500 khz auto mode figure 68. lm73605-q1 dropout curve vin (v) output voltage (v) 4 4.4 4.8 5.2 5.6 6 6.4 6.8 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 do_5 load = 1.5ma load = 1a load = 3a load = 5a vin (v) output voltage (v) 4 4.4 4.8 5.2 5.6 6 6.4 6.8 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 do_5 load = 1.5ma load = 1a load = 3a load = 5a vin (v) output voltage (v) 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 do_3 load = 1.5ma load = 1a load = 3a load = 5a vin (v) output voltage (v) 3.5 4 4.5 5 5.5 6 6.5 7 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 do_3 load = 1.5 ma load = 1.5 a load = 3 a load = 6 a vin (v) output voltage (v) 11 11.4 11.8 12.2 12.6 13 13.4 13.8 10 10.2 10.4 10.6 10.8 11 11.2 11.4 11.6 11.8 12 12.2 12.4 12.6 12.8 13 do_1 load = 1.5ma load = 1a load = 3a load = 5a vin (v) output votlage (v) 3.5 4 4.5 5 5.5 6 6.5 7 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 do_3 load = 1.5 ma load = 1.5 a load = 3 a load = 6 a
39 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated v in = 12 v v out = 3.3 v f sw = 500 khz i out = 1 ma auto mode figure 69. lm73606-q1 switching waveform and v out ripple v in = 12 v v out = 3.3 v f sw = 500 khz i out = 1 ma fpwm mode figure 70. lm73606-q1 switching waveform and v out ripple v in = 12 v v out = 3.3 v f sw = 500 khz i out = 100 ma auto mode figure 71. lm73606-q1 switching waveform and v out ripple v in = 12 v v out = 3.3 v f sw = 500 khz i out = 100 ma fpwm mode figure 72. lm73606-q1 switching waveform and v out ripple v in = 12 v v out = 3.3 v f sw = 500 khz i out = 6 a auto mode figure 73. lm73606-q1 switching waveform and v out ripple v in = 3.66 v v out = 3.3 v f sw set at 500 khz i out = 3 a auto mode figure 74. lm73606-q1 switching waveform at dropout v out ripple v sw (1 a/div) time (5 s/div) i inductor (20 mv/div) (5 v/div) v out ripple v sw (2 a/div) time (2 s/div) i inductor (20 mv/div) (5 v/div) v out ripple v sw (1 a/div) time (2 s/div) i inductor (20 mv/div) (5 v/div) v out ripple v sw (1 a/div) time (500 s/div) i inductor (20 mv/div) (5 v/div) v out ripple v sw (1 a/div) time (5 s/div) i inductor (20 mv/div) (5 v/div) v out ripple v sw (1 a/div) time (5 s/div) i inductor (20 mv/div) (5 v/div)
40 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated v in = 12 v v out set at 3.3 v f sw set at 500 khz i out = 7.5 a v out droops to 2 v figure 75. lm73606-q1 overcurrent behavior v in = 12 v v out = 3.3 v f sw = 500 khz figure 76. lm73606-q1 short-circuit hiccup protection and recovery v in = 12 v v out = 3.3 v f sw = 500 khz i out = 200 ma fpwm mode figure 77. lm73606-q1 soft start with 200-ma load in fpwm mode v in = 12 v v out = 3.3 v f sw = 500 khz i out = 200 ma auto mode figure 78. lm73606-q1 soft start with 200-ma load in auto mode v in = 12 v v out = 3.3 v f sw = 500 khz i out = 5 a auto mode figure 79. lm73606-q1 soft start with 5-a load v in = 12 v v out = 3.3 v f sw = 500 khz v pre-bias = 1.5 v auto mode figure 80. lm73606-q1 soft start with pre-biased output voltage v out enable (2 a/div) time (2 ms/div) i inductor (2 v/div) (5 v/div) (10 v/div) pgood v out enable (2 a/div) time (2 ms/div) i inductor (2 v/div) (5 v/div) (10 v/div) pgood v out v sw (2 a/div) time (50 ms/div) i inductor (1 v/div) (5 v/div) v out v sw (2 a/div) time (5 s/div) i inductor (1 v/div) (5 v/div) v out enable (2 a/div) time (2 ms/div) i inductor (2 v/div) (5 v/div) (5 v/div) pgood v out enable (2 a/div) time (2 ms/div) i inductor (2 v/div) (5 v/div) (5 v/div) pgood
41 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated v in = 12 v v out = 3.3 v f sw = 500 khz i out = 10 ma to 6 a to 10 ma auto mode figure 81. lm73606-q1 load transients v in = 12 v v out = 3.3 v f sw = 500 khz i out = 10 ma to 6 a to 10 ma fpwm mode figure 82. lm73606-q1 load transients v in = 12 v v out = 5 v f sw = 2200 khz i out = 10 ma to 5 a to 10 ma auto mode figure 83. lm73605-q1 load transients v in = 12 v v out = 5 v f sw = 2200 khz i out = 10 ma to 5 a to 10 ma fpwm mode figure 84. lm73605-q1 load transients i out = 100 ma v out = 3.3 v f sw = 500 khz v in = 10 v to 35 v to 10 v auto mode figure 85. lm73606-q1 line transients i out = 2 a v out = 3.3 v f sw = 500 khz v in = 10 v to 35 v to 10 v auto mode figure 86. lm73606-q1 line transients v out v in (2 a/div) time (200 s/div) i inductor (200 mv/ div) (20 v/div) v out v in (2 a/div) time (200 s/div) i inductor (200 mv/ div) (20 v/div) v out (5 a/div) time (200 s/div) i inductor (500 mv/ div ac) (5 a/div) i out v out (5 a/div) time (200 s/div) i inductor (500 mv/ div ac) (5 a/div) i out v out (5 a/div) time (200 s/div) i inductor (200 mv/ div ac) (5 a/div) i out v out (5 a/div) time (200 s/div) i inductor (200 mv/ div ac) (5 a/div) i out
42 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated v in = 12 v v out = 5 v i out = 4 a f sw = 400 khz tested on lm73606evm-5v-400k c flt = 4 4.7 f l in = 1 h c bulk = 10 f figure 87. lm73606-q1 conducted emi result vs. cispr25 limits - low frequency v in = 12 v v out = 5 v i out = 4 a f sw = 400 khz tested on lm73606evm-5v-400k c flt = 4 4.7 f l in = 1 h c bulk = 10 f figure 88. lm73606-q1 conducted emi result vs. cispr25 limits - high frequency v in = 13.5 v v out = 5 v i out = 3.5 a f sw = 2.2 mhz tested on lm73605evm-5v-2mhz c flt = 3 2.2 f l in = 0.6 h c bulk = 10 f cm choke = acm1211-102-2pl-tl01 c choke = 2 2.2 f figure 89. lm73606-q1 conducted emi result vs. cispr25 limits - low frequency v in = 13.5 v v out = 5 v i out = 3.5 a f sw = 2.2 mhz tested on lm73605evm-5v-2mhz c flt = 3 2.2 f l in = 0.6 h c bulk = 10 f cm choke = acm1211-102-2pl-tl01 c choke = 2 2.2 f figure 90. lm73606-q1 conducted emi result vs. cispr25 limits - high frequency peak value average value vhf1-pk5 vhf2-pk5 tvi-pk5 fm-pk5 vhf1-av5 vhf2-av5 tvi-av5 fm-av5 peak value average value vhf1-pk5 vhf2-pk5 tvi-pk5 fm-pk5 vhf1-av5 vhf2-av5 tvi-av5 fm-av5 v out ripple v sw (1 a/div) time (500 s/div) i inductor (20 mv/div) (5 v/div) peak value average value lw_pk5 cb_pk5 lw_av5 mw_pk5 mw_av5 sw_pk5 sw_av5 cb_av5 peak value average value lw_pk5 cb_pk5 lw_av5 mw_pk5 mw_av5 sw pk5 sw av5 cb_av5
43 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated v in = 13.5 v v out = 5 v i out = 5 a f sw = 400 khz tested on lm73606evm-5v-400k c flt = 3 2.2 f l in = 1 h c bulk = 10 f figure 91. lm73606-q1 radiated emi result vs. cispr25 limits - low frequency v in = 13.5 v v out = 5 v i out = 5 a f sw = 400 khz tested on lm73606evm-5v-400k c flt = 3 2.2 f l in = 1 h c bulk = 10 f figure 92. lm73606-q1 radiated emi result vs. cispr25 limits - high frequency v in = 13.5 v v out = 5 v i out = 3 a f sw = 2200 khz tested on lm73605evm-5v-2mhz c flt = 3 2.2 f l in = 0.6 h c bulk = 10 f cm choke = acm1211-102-2pl-tl01 c choke = 2 2.2 f figure 93. lm73606-q1 radiated emi result vs. cispr25 limits - low frequency v in = 13.5 v v out = 5 v i out = 3 a f sw = 2200 khz tested on lm73605evm-5v-2mhz c flt = 3 2.2 f l in = 0.6 h c bulk = 10 f cm choke = acm1211-102-2pl-tl01 c choke = 2 2.2 f figure 94. lm73606-q1 radiated emi result vs. cispr25 limits - high frequency 10 15 20 25 30 35 40 45 50 200 300 400 500 600 700 800 900 1000 level in dbv/m frequency (mhz) peak_limit peak detector _vertical_log peak detector _horizontal_log 10 15 20 25 30 35 40 45 50 200 300 400 500 600 700 800 900 1000 level in dbv/m frequency (mhz) peak_limit peak detector _vertical_log peak detector _horizontal_log 0 5 10 15 20 25 30 35 40 45 50 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 level in dbv/m frequency(mhz) peak_limit avg_limit peak detector _vertical_bicon peak detector _horizontal_bicon 0 5 10 15 20 25 30 35 40 45 50 30 50 70 90 110 130 150 170 190 level in dbv/m frequency(mhz) peak_limit avg_limit peak detector_vertical_bicon peak detector_horizontal_bicon
44 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 9 power supply recommendations the lm73605-q1/6-q1 is designed to operate from an input voltage supply range from 3.5 v to 36 v. this input supply must be able to withstand the maximum input current and maintain a voltage above 3.5 v at the pvin pin. the resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the lm73605-q1/6-q1 supply voltage that can cause a false uvlo fault triggering and system reset. if the input supply is located more than a few inches from the lm73605-q1/6-q1, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. a 47- f or 100- f electrolytic capacitor is a typical choice. 10 layout 10.1 layout guidelines the performance of any switching converter depends heavily upon the layout of the pcb. use the following guidelines to design a pcb layout with optimum power conversion performance, emi performance, and thermal performance. 1. place ceramic high frequency bypass capacitors as close as possible to the pvin and pgnd pins, which are right next to each other on the package. place the small value ceramic capacitor closest to the pins. this is very important for emi performance. 2. use short and wide traces, or localized ic layer planes, for high current paths, such as v in , v out , sw and gnd connections. short and wide copper traces reduce power loss and noise due to low parasitic resistance and inductance. wide copper traces also help reduce die temperature, because they also provide wide heat dissipation paths. use thick copper (2 oz) on high current layer(s) if possible. 3. confine pulsing current paths (v in , sw, and ground return for v in ) on the device layer as much as possible to prevent switching noises from contaminating other layers. 4. c boot capacitor also contains pulsing current. place c boot close to the pin and route to sw with short trace. the pinout of the device makes it easy to optimize the c boot placement and routing. 5. use a solid ground plane at the layer right underneath the device as a noise shielding and heat dissipation path. 6. place the vcc bypass capacitor close to the vcc pin. tie the ground pad of the capacitor to the ground plane using a via right next to it. 7. use via next to agnd pin to the ground plane. 8. minimize trace length to the fb pin. both feedback resistors must be located right next to the fb pin. tie the ground side of r fbb to the ground plane with a via right next to it. place c ff directly in parallel with r fbt if used. 9. if v out accuracy at the load is important, make sure the v out sense point is made close to the load. route v out sense to r fbt through a path away from noisy nodes and preferably on a layer on the other side of the ground plane. if bias is connected to v out , do not use the same trace to route v out to bias and to r fbt . bias current contains pulsing driver current and it changes with operating mode. use separated traces for bias and v out sense to optimize v out regulation accuracy. 10. provide adequate device heat sinking. use an array of heat-sinking vias to connect the exposed pad to the ground plane and the bottom pcb layer. connect the dap and nc pins on the short sides of the device to the gnd net, so that ic layer ground copper can provide an optimal dog-bone shape heat sink. heat generated on the die can flow directly from device junction to the dap then to the copper and spread to the wider copper outside of the device. try to keep copper area solid on the top and bottom layer around thermal vias on the dap to optimize heat dissipation.
45 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated layout guidelines (continued) 10.1.1 layout for emi reduction to optimize emi performance, place the components in the high di/dt current path, as shown in figure 95 , as close as possible to each other. when the components are close to each other, the area of the loop enclosed by these components, and the parasitic inductance of this loop, are minimized. the noises generated by the pulsing current and parasitic inductances are then minimized. figure 95. pulsing current path of buck converter in a buck converter, the high di/dt current path is composed of the hs and ls mosfets and the input capacitors. because the two mosfets are integrated inside the device, they are closer to each other than in discrete solutions. pvin and pgnd pins are the connections from the mosfets to the input capacitors. the first step of the layout must be placing the input capacitors, especially the small value ceramic bypass one, as close as possible to pvin and pgnd pins. the lm73605-q1/6-q1 pinout is optimized for low emi layout. multiple pins are used for pvin and pgnd to minimized bond wire resistances and inductances. the pvin and pgnd pins are right next to each other to simplify optimal layout. the cboot pin is placed next to sw pin for easy and compact c boot capacitor layout. 10.1.2 ground plane the ground plane of a pcb provides the best return path for the pulsing current on the device layer. make sure the ground plane is solid, especially the part right underneath the pulsing current paths. solid copper under a pulsing current path provide a mirrored return path for the high frequency components and minimize voltage spikes generated by the pulsing current. it shields the layers on the other side of the plane from switching noises. route signal traces on the other side of the ground plane as much as possible. use multiple vias in parallel to connect the grounds on the device layer to the ground plane. 10.1.3 optimize thermal performance the key to thermal optimization on pcb design is to provide heat transferring paths from the device to the outer large copper area. use thick copper (2 oz) on high current layer(s) if possible. use thermal vias under the dap to transfer heat to other layers. connect nc pins to the gnd net, so that gnd copper can run underneath the device to create dog-bone shape heat sink. try to leave copper solid on ic side as much as possible above and below the device. place components and route traces away from major heat transferring paths if possible, to avoid blocking heat dissipation path. try to leave copper solid, free of components and traces, around the thermal vias on the other side of the board as well. solid copper behaves as heat sink to spread the heat to a larger area and provide more contact area to the air. when calculating power dissipation, use the maximum input voltage and the average output current for the application. many common operating conditions are provided in application curves . less common applications can be derived through interpolation. in all designs, the junction temperature must be kept below the rated maximum of 125 c. sw vin pgnd pgnd c in v in c out v out l high di/dt current buck converter
46 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated layout guidelines (continued) the thermal characteristics of the lm73605-q1/6-q1 are specified using the parameter r ja , which characterize thermal resistance from the junction of the silicon to the ambient in a specific system. although the value of r ja is dependant on many variables, it still can be used to approximate the operating junction temperature of the device. to obtain an estimate of the device junction temperature, one may use equation 30 : t j = p ic_loss r ja + t a where ? t j = junction temperature in c ? p ic_loss = v in i in (1 ? efficiency) ? 1.1 i out dcr ? dcr = inductor dc parasitic resistance in ? r ja = junction-to-ambient thermal resistance of the device in c/w ? t a = ambient temperature in c. (30) the maximum operating junction temperature of the lm73605-q1/6-q1 is 125 c. r ja is highly related to pcb size and layout, as well as environmental factors such as heat sinking and air flow. figure 96 shows measured results of r ja with different copper area on 2-layer boards and 4-layer boards, with 1-w and 2-w power dissipation on the lm73605-q1/6-q1. figure 96. measured r ja vs pcb copper area on 2-layer boards and 4-layer boards 10 12 14 16 18 20 22 24 26 28 30 20 30 40 50 60 70 80 1w @0 fpm - 2layer 1w @0 fpm - 4layer 2w @0 fpm - 2layer 2w @0 fpm - 4layer copper area r , ja (c/w) 30mm 30mm 40mm 40mm 50mm 50mm 70mm 70mm
47 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 10.2 layout example a layout example is shown in figure 97 . a four-layer board is used with 2-oz copper on the top and bottom layers and 1-oz copper on the inner two layers. figure 97 shows the relative scale of the lm73605-q1/6-q1 device with 0805 and 1210 input and output capacitors, 7-mm 7-mm inductor and 0603 case size for all other passive components. the trace width of the signal connections are not to scale. the components are placed on the top layer and the high current paths are routed on the top layer as well. the remaining space on the top layer can be filled with gnd polygon. thermal vias are used under the dap and around the device. the gnd copper was extended to the outside of the device, which serves as copper heat sink. the mid-layer 1 is right underneath the top layer. it is a solid ground plane, which serves as noise shielding and heat dissipation path. the v out sense trace is routed on the 3rd layer, which is mid-layer 2. ground plane provided noise shielding for the sense trace. the v out to bias connection is routed by a separate trace. the bottom layer is also a solid ground copper in this example. solid copper provides best heat sinking for the device. if components and traces need to be on the bottom layer, leave the area around thermal vias as solid as possible. try not to cut heat dissipation path by a trace. the board can be used for various frequencies and output voltages, with component variation. for more details, see the lm73605/lm73606 evm user ' s guide . figure 97. lm73605-q1/6-q1 layout example
48 lm73605-q1 , lm73606-q1 snvsb12 ? november 2017 www.ti.com product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 11 device and documentation support 11.1 device support 11.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 11.1.2 custom design with webench ? tools click here to create a custom design using the lm73605-q1 or lm73606-q1 device with the webench ? power designer. 1. start by entering the input voltage (v in ), output voltage (v out ), and output current (i out ) requirements. 2. optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. compare the generated design with other possible solutions from texas instruments. the webench power designer provides a customized schematic along with a list of materials with real-time pricing and component availability. in most cases, these actions are available: ? run electrical simulations to see important waveforms and circuit performance ? run thermal simulations to understand board thermal performance ? export customized schematic and layout into popular cad formats ? print pdf reports for the design, and share the design with colleagues get more information about webench tools at www.ti.com/webench . 11.2 related documentation for related documentation see the following: an-2020 thermal design by insight, not hindsight 11.3 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to order now. table 5. related links parts product folder order now technical documents tools & software support & community lm73605-q1 click here click here click here click here click here lm73606-q1 click here click here click here click here click here 11.4 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document.
49 lm73605-q1 , lm73606-q1 www.ti.com snvsb12 ? november 2017 product folder links: lm73605-q1 lm73606-q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 11.5 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.6 trademarks e2e is a trademark of texas instruments. webench is a registered trademark of texas instruments. sp-cap is a trademark of panasonic. poscap is a trademark of sanyo electric co., ltd.. 11.7 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.8 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 20-dec-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples LM73605QRNPRQ1 active wqfn rnp 30 3000 green (rohs & no sb/br) cu sn level-2-260c-1 year -40 to 125 lm73605r npq1 lm73605qrnptq1 active wqfn rnp 30 250 green (rohs & no sb/br) cu sn level-2-260c-1 year -40 to 125 lm73605r npq1 lm73606qrnprq1 active wqfn rnp 30 3000 green (rohs & no sb/br) cu sn level-2-260c-1 year -40 to 125 lm73606r npq1 lm73606qrnptq1 active wqfn rnp 30 250 green (rohs & no sb/br) cu sn level-2-260c-1 year -40 to 125 lm73606r npq1 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 20-dec-2017 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant LM73605QRNPRQ1 wqfn rnp 30 3000 330.0 16.4 4.25 6.25 0.95 8.0 16.0 q1 lm73605qrnptq1 wqfn rnp 30 250 180.0 16.4 4.25 6.25 0.95 8.0 16.0 q1 lm73606qrnprq1 wqfn rnp 30 3000 330.0 16.4 4.25 6.25 0.95 8.0 16.0 q1 lm73606qrnptq1 wqfn rnp 30 250 180.0 16.4 4.25 6.25 0.95 8.0 16.0 q1 package materials information www.ti.com 20-dec-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) LM73605QRNPRQ1 wqfn rnp 30 3000 370.0 355.0 55.0 lm73605qrnptq1 wqfn rnp 30 250 195.0 200.0 45.0 lm73606qrnprq1 wqfn rnp 30 3000 370.0 355.0 55.0 lm73606qrnptq1 wqfn rnp 30 250 195.0 200.0 45.0 package materials information www.ti.com 20-dec-2017 pack materials-page 2
a a www.ti.com package outline c 30x 0.3 0.2 2.2 0.1 22x 0.65 0.45 0.8 max (0.2) typ 0.05 0.00 26x 0.5 2x 5 4.6 0.1 2x 1.5 8x 0.5 0.3 a 4.1 3.9 b 6.1 5.9 0.1 min (0.05) wqfn - 0.8 mm max height rnp0030a plastic quad flatpack - no lead 4222145/b 09/2017 pin 1 index area 0.08 seating plane 1 11 16 26 12 15 30 27 (optional) pin 1 id 0.1 c a b 0.05 exposed thermal pad symm symm notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. the package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. scale 2.700 scale 25.000 section a-a section a-a typical
www.ti.com example board layout 0.07 min all around 0.07 max all around 30x (0.25) 22x (0.75) ( 0.2) typ via (r0.05) typ 2x (2.05) (5.8) (3.65) (0.5) typ (2.2) 6x (0.85) 6x (1.16) (4.6) 8x (0.6) wqfn - 0.8 mm max height rnp0030a plastic quad flatpack - no lead 4222145/b 09/2017 symm 1 11 12 15 16 26 27 30 symm land pattern example scale:15x notes: (continued) 4. this package is designed to be soldered to a thermal pad on the board. for more information, see texas instruments literature number slua271 (www.ti.com/lit/slua271). solder mask opening metal under solder mask solder mask defined metal solder mask opening solder mask details non solder mask defined (preferred)
www.ti.com example stencil design 22x (0.75) 30x (0.25) 26x (0.5) (3.65) (5.8) 8x (0.98) (1.16) typ (0.59) typ (r0.05) typ 8x (0.96) 8x (0.6) (0.58) typ wqfn - 0.8 mm max height rnp0030a plastic quad flatpack - no lead 4222145/b 09/2017 notes: (continued) 5. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. symm metal typ solder paste example based on 0.125 mm thick stencil exposed pad 74.4% printed solder coverage by area scale:20x symm 1 11 12 15 16 26 27 30
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